1. Field of the Invention
The present invention relates to a method of manufacturing a semiconductor device, more particularly, to a method of manufacturing a semiconductor device composed of a plurality of layers.
2. Related Background Art
Conventionally, in a method of manufacturing a semiconductor device having a large chip size and a fine pattern, the pattern of each layer (hereinafter referred to as an “original pattern”) is divided into a plurality of patterns (hereinafter referred to as “divided patterns”), and an original pattern on a layer is formed by joining the divided patterns to be exposed (hereinafter referred to as “split exposure”). These processes are repeated several times to manufacture a semiconductor device composed of a plurality of layers (see, for example, U.S. Pat. No. 5,561,317, and U.S. Pat. No. 5,731,131).
FIG. 6 is a plan view showing the structure of a part of a semiconductor device manufactured by the conventional manufacturing method. With reference to FIG. 6, the semiconductor device 90 includes an active region 91, polysilicon layers 92, contact holes 93 and metal layers 94 and 95. Here, the structure of a pixel of a semiconductor device to be used in an image pickup apparatus such as a digital camera, or the like, is exemplified.
The active region 91 becomes a photoelectric conversion portion.
The polysilicon layers 92 become gate electrodes of a metal oxide semiconductor field effect transistor (MOS FET). The contact holes 93 become electrodes connecting layers. The metal layers 94 and 95 become wiring.
In the actual semiconductor device 90, a plurality of pattern, one of which is shown in FIG. 6, is continuously formed in the upper and lower directions and the right and left directions.
A section (a) and a section (b) of FIG. 7 are views for illustrating the method of manufacturing the semiconductor device shown in FIG. 6. The section (a) of FIG. 7 shows a plan view of the semiconductor device. The section (b) of FIG. 7 shows a sectional view taken on an A–A′ line in the plan view.
With reference to the section (a) of FIG. 7, the patterns repeating a pattern in the upper and the lower directions and the right and the left directions are formed on the semiconductor device 90. The repeating patterns of each layer are set as an original pattern and are divided into a plurality of divided patterns. Then, the divided patterns are joined with each other to form the pattern of each layer. An X–X′ line in the sections (a) and (b) of FIG. 7 indicates a joint between the divided patterns.
In the method of manufacturing the semiconductor device 90 shown in FIG. 6, and the sections (a) and (b) of FIG. 7, a thermal oxidation film and a SiN film are first formed on a silicon substrate (not shown), and the films are processed by dry etching with a mask having a predetermined pattern to leave the patterns of the active regions 91. After the formation of the active regions 91, next, a local oxidation of silicon (LOCOS) film (not shown) is formed by thermal oxidation processing.
Next, an ion implantation is performed with a mask having a predetermined pattern to form a predetermined diffusion layer.
Next, a film of polysilicon is formed, and the dry etching with a mask having a predetermined pattern of the polysilicon film is performed to form the polysilicon layers 92 being the gate electrodes of the MOS FET's. After the formation of the polysilicon layers 92, an interlayer insulation film (not shown) is formed.
Next, the contact holes 93 are formed in the interlayer insulation film with a mask having a predetermined pattern.
Next, an Al—Cu film is formed, and the dry etching of the Al—Cu film is performed with a mask having a predetermined pattern to form first layer metal layers 94. After the formation of the metal layers 94, an interlayer insulation film (not shown) is formed, and through holes are formed in the interlayer insulation film.
Next, an Al—Cu film is formed, and the dry etching of the Al—Cu film is performed with a mask having a predetermined pattern to form second layer metal layers 95.
The patterns of these respective layers, including the polysilicon layers 92, are formed by division exposure using the X–X′ line as a joint. The split exposure is performed by repeating the formation of a divided pattern and a movement of the silicon substrate by the step and repeat method. In the division exposure, alignment to a ground (hereinafter referred to as “alignment”) using an alignment mark formed on the ground as a landmark is performed before forming each divided pattern. In the division exposure, focusing may be performed to each divided pattern (see, for example, the abstract of Japanese Patent Application Laid-Open No. H04-326507). Moreover, the example of the division exposure in which all of the patterns of respective layers are exposed by the use of the same X–X′ line as the joint is shown here, but the joint of each layer may be shifted (see, for example, U.S. Pat. No. 6,204,912).
By the manufacturing method described above, a semiconductor device having a large chip size and fine patterns can be easily manufactured.
In the split exposure, each divided pattern is aligned by the alignment. However, the alignment includes errors (hereinafter referred to as “alignment errors”) to some degree. Consequently, there is a case wherein discrepancies are produced among the divided patterns of respective layers at the X–X′ line in the section (a) of FIG. 7.
The shape of the polysilicon layer at the cross section at the A–A′ line is shown in the section (b) of FIG. 7.
When there is a discrepancy between divided patterns, an interval “a′” between gate electrodes 81 and 82, which are made of polysilicon in two divided patterns adjoining the X–X′ line, is not equal to a distance “a”. Incidentally, the example of a′<a is shown in the section (b) of FIG. 7, but it is naturally possible for this to be a′>a. On the other hand, there is no joint of divided patterns between gate electrodes 83 and 84. Consequently, no discrepancy is produced between the gate electrodes 83 and 84.
Moreover, parasitic capacitance is generated between close electrodes or wiring, and the value of the capacitance differs according to the distance between them even if the shapes of them are the same. Consequently, the capacitance formed over a joint has a different value from the value of the capacitance formed between things without any joint between them. In an image pickup apparatus, or the like, the capacitance difference appears as an output difference between pixels to generate a stripe on a screen, in some cases. In particular, when a discrepancy owing to a joint is produced between adjoining electrodes (wiring) in the layers (hereupon, the polysilicon layers) to be used as the control electrodes (wiring) of MOS FET's, which amplify and transfer signals and thereby, the parasitic capacitance differs, the difference frequently causes a big problem.